AMD Ramps 6th Gen EPYC "Venice" On TSMC 2nm, Plans Follow-On "Verano" With LPDDR Memory Integration

Advanced Micro Devices, Inc.

Advanced Micro Devices, Inc.

AMD

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  • AMD has begun production ramp of its 6th Gen AMD EPYC™ CPUs, codenamed "Venice," marking a major milestone for the AMD and TSMC collaboration on 2nm technology
  • "Venice" is the first HPC product in the industry to achieve production ramp on TSMC advanced 2nm technology
  • Critical milestone achieved as agentic AI workloads drive demand for accelerated AI infrastructure deployments
  • AMD continues to drive 2nm product expansion with "Verano" a follow on to "Venice" with industry leading integration of LPDDR for growing memory demand in agentic AI workloads
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