Synopsys Unveils Software-Defined Hardware-Assisted Verification for AI Chips
Synopsys, Inc. SNPS | 395.95 | -0.20% |
Synopsys Inc. announced new research and development results across its hardware-assisted verification portfolio, introducing a software-defined approach that can deliver up to 2x performance for ZeBu Server 5 and up to 2x capacity scaling with modular HAV for large AI-era chip designs. The company also unveiled new HAPS-200 and ZeBu-200 12-FPGA platforms using AMD Versal Premium VP1902 adaptive SoCs, plus new hardware-assisted test automation aimed at earlier detection of cache-coherency and subsystem-level bugs. These results were already presented as part of the announcement, with the new HAPS-200 12-FPGA platform available now and the ZeBu-200 12-FPGA platform slated for Q3 2026.
Disclaimer: This news brief was created by Public Technologies (PUBT) using generative artificial intelligence. While PUBT strives to provide accurate and timely information, this AI-generated content is for informational purposes only and should not be interpreted as financial, investment, or legal advice. Synopsys Inc. published the original content used to generate this news brief via PR Newswire (Ref. ID: SF07827) on March 11, 2026, and is solely responsible for the information contained therein.
