TSMC Delays High NA EUV As It Balances Costs And Chip Progress

Taiwan Semiconductor Manufacturing Co., Ltd. Sponsored ADR

Taiwan Semiconductor Manufacturing Co., Ltd. Sponsored ADR

TSM

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  • TSMC (NYSE:TSM) plans to delay deploying ASML's most advanced high numerical aperture EUV lithography machines until 2029.
  • The company intends to focus on alternative technologies and process optimizations to improve chip power and efficiency without immediately adopting these higher cost tools.
  • The decision affects TSMC's long term technology roadmap, capital spending profile, and relationships across the semiconductor equipment supply chain.

For you as an investor, this sits at the core of what TSMC does. The company is a leading contract chip manufacturer, supplying advanced processors to a wide range of customers that depend on cutting edge production capabilities. The choice to prioritize other approaches over high NA EUV equipment touches on long term questions around cost control, manufacturing complexity, and competitive positioning at the leading edge of chip design.

Looking ahead, the key issues to watch include how effectively TSMC can sustain performance and efficiency gains using its chosen toolkit and how this timing interacts with customer roadmaps. The decision may also influence spending plans for major equipment vendors and rival foundries, which could shape capacity, pricing power, and industry partnerships over the rest of this decade.

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NYSE:TSM Earnings & Revenue Growth as at Apr 2026
NYSE:TSM Earnings & Revenue Growth as at Apr 2026

This decision pushes the most expensive high-NA EUV tools further out, which can help TSMC smooth capital spending and keep unit costs in check on advanced nodes. For customers designing AI and high performance chips, what matters is whether TSMC can keep shrinking features and improving power efficiency using existing EUV tools, advanced packaging, and process tweaks. Intel and Samsung are investing heavily in their own leading edge processes, so any perception that TSMC is slowing tool adoption could shape how those competitors position themselves with large customers. At the same time, holding off on high-NA EUV may reduce near term dependence on a single equipment vendor and give TSMC more flexibility to match capacity decisions with actual demand for 2 nm and beyond.

The Risks and Rewards Investors Should Consider

  • ⚠️ Waiting until 2029 for high-NA EUV could allow rivals like Intel and Samsung to market earlier access to that technology, which may influence future orders at the very leading edge.
  • ⚠️ Relying on process optimizations rather than new tools raises execution risk if power or performance gains prove harder to achieve than planned on upcoming nodes.
  • 🎁 Spreading out high-NA EUV spending may support capital discipline, which can be important for margins and cash generation if industry demand becomes less robust.
  • 🎁 The focus on alternative methods to raise chip power and efficiency fits with TSMC’s role in AI and advanced compute supply chains, where customers value consistent output and reliable roadmaps as much as headline tool adoption.

What To Watch Going Forward

From here, it will be important to follow how TSMC describes performance and yield targets for its next nodes, especially 2 nm and the planned A13 process in 2029, and how that compares with commentary from Intel and Samsung. Customer comments on foundry diversification, AI chip roadmaps, and long term capacity plans will help show whether the timing of high-NA EUV affects TSMC’s share of advanced designs. Any updates to capital expenditure guidance, or shifts in equipment orders with key suppliers, will also be useful signals for how this choice flows through to costs and future capacity.

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